1. Technical Field
The present invention relates to a flash memory device, and more particularly, to a flash memory device capable of variably controlling a program voltage and a method of programming the flash memory device.
2. Discussion of the Related Art
One of the main issues in developing semiconductor memory devices is to maximize data storage capacity. Data storage capacity can be increased by increasing the number of bits of data that can be stored per unit area, and accordingly, memory chips have been developed that can store large amounts of data in a minimum area. One technique for increasing the data storage capacity of a memory chip involves storing multiple levels of charge in each memory cell. Memory chips that employ this technique are known as “multi-level” memory chips.
One type of semiconductor memory device is a flash memory device. Flash memory devices are capable of retaining data even in the absence of power. In flash memory devices, data programming and erasing may be achieved using a tunneling phenomenon. Flash memory devices are suitable for use as auxiliary storage devices due to their excellent data storage capability, low power consumption, and high durability to external shocks. There are two types of flash memory devices, NAND flash memory and NOR flash memory. The size of a memory cell in a NAND flash memory device in which a fixed number of memory cells are connected in series is smaller than the size of a memory cell in a NOR flash memory device in which memory cells are connected in parallel. Accordingly, the NAND flash memory device has excellent integration and thus is more suitable for use as a high-capacity auxiliary storage device.
Unlike the NAND flash memory device having single level cells, the NAND flash memory device having multi-level cells stores 2 bits of data in one cell and is characterized by four states, as illustrated in FIG. 1. FIG. 1 shows a threshold voltage distribution of the four states. An unprogrammed state is characterized by a distribution below a first read voltage VR1. A first programmed state is characterized by a distribution between PV1 and PV1′. A second programmed state is characterized by a distribution between PV2 and PV2′. A third programmed state is characterized by a distribution between PV3 and PV3′. However, when the distribution between PV1 and PV1′, the distribution between PV2 and PV2′, and the distribution between PV3 and PV3′ are widened, an interval between PV1′ and PV2 and an interval between PV2′ and PV3 are narrowed. The narrowed intervals between the programmed states make it more likely that a programmed memory cell is incorrectly read and accordingly, memory cell reliability is reduced. Thus, an increase of the threshold voltage distribution of programmed cells is used for multi-level cells.
The threshold voltage distribution of the NAND flash memory device may be accurately controlled by using an Increment Step Pulse Programming (hereinafter, referred to as “ISPP”) method. In the ISPP method, the program voltage is increased in stages by a determined increment by a repetition of program loops of a program cycle. As a programming operation progresses, the threshold voltages of the programmed cells are increased by an increment determined in each program loop. Accordingly, the increment of the program voltage is small to allow for the threshold distributions of programmed cells to be narrow in width. However, when the increment of the program voltage decreases, the number of program loops increases. Thus, programming characteristics worsen.